Micrel
Values
MICRF506BML/YML
Symbol
Tper
Thigh
Tlow
tfall
trise
Tcsr
Parameter
Min. period of
SCLK
Min. high time of
SCLK
Min. low time of
SCLK
Max. time of
falling edge of
SCLK
Max. time of rising
edge of SCLK
Max. time of rising
Min.
50
20
20
0
Typ.
Max.
1
1
Units
ns
ns
ns
μs
μs
ns
Power on Reset
When applying voltage to the MICRF506 a power
on reset state is entered. During the time period of
power on reset, the MICRF506 should be
considered to be in an unknown state and the user
should wait until completed (See Table 6). The
power on reset timing given in table 6 is covering all
conditions and should be treated as a maximum
delay time. In some application it might be beneficial
to minimize the power on reset time. In these cases
we recommend to follow below procedure:
edge of CS to
falling edge of
SCLK
Tcsf
Min. delay from
5
ns
rising edge of CS
to rising edge of
SCLK
Twrite
Min. delay from
0
ns
valid IO to falling
edge of SCLK
during a write
operation
Tread
Min. delay from
75
ns
rising edge of
SCLK to valid IO
during a read
operation
(assuming load
capacitance of IO
is 25pF)
Table 6. Timing Specification for the 3-wire
Programming Interface
July 2006
13
M9999-092904
+1 408-944-0800
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